Width scalable connector for high bandwidth IO interfaces

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United States of America Patent

PATENT NO 9106217
SERIAL NO

13977050

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Abstract

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Disclosed is a scalable input/output interface that has multiple bays and includes a housing surrounding a plurality of pairs of substrates. A first substrate of the pair of substrates may have a first contact surface and a second substrate of the pair of substrates may have a second contact surface that opposes the first contact surface, wherein each substrate has a connection edge. At least one integrated buffer can be coupled to either the first side or the second side of each substrate. A plurality of rows of contacts can be coupled to the opposing surfaces of each substrate of the pair of substrates, wherein each row of contacts can be stacked substantially parallel to the connection edge. Each connection edge can also be coupled to a separate integrated buffer.

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Patent Owner(s)

  • INTEL CORPORATION

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Heck, Howard L Hillsboro, US 36 305
Jaussi, James E Hillsboro, US 93 1405
Mooney, Stephen R Mapleton, US 97 1871
Pederson, Bruce E Beaverton, US 3 6

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