Single wire serial interface master module and method thereof for sampling data information
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United States of America Patent
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Mar 7, 2017
Grant Date -
Jul 3, 2014
app pub date -
Nov 25, 2013
filing date -
Dec 31, 2012
priority date (Note) -
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Abstract
The present invention discloses a single wire serial interface (SSI) master module, including: a sample delay controlling unit, configured to send a delay instruction; the state machine unit, configured to wait, according to the delay instruction, for a delay period starting from a moment when an SSI master module completes sending the last bit of address information in a read operation frame, and then send a sample control signal to a selector unit; the selector unit, configured to enable a transmission channel with a sampling unit after receiving the sample control signal; and the sampling unit, configured to sample data information from an SSI slave module. In the present invention, the state machine unit delays sending the sample control signal, and the sampling unit is controlled to delay sampling the data information, which avoids a data reception error caused by slow discharging of an IO PAD.
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