System and method for conveying service latency requirements for devices connected to low power input/output sub-systems

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United States of America Patent

PATENT NO 9158357
APP PUB NO 20140189391A1
SERIAL NO

13730625

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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In at least one embodiment described herein, an apparatus is provided that can include means for communicating a latency tolerance value for a device connected to a platform from a software latency register if a software latency tolerance register mode is active. The apparatus may also include means for communicating the latency tolerance value from a hardware latency register if a host controller is active. The latency tolerance value can be sent to a power management controller. More specific examples can include means for communicating a latency tolerance value from the software latency register if the software latency tolerance register mode is not active and the host controller is not active. The apparatus can also include means for mapping a resource space in the software latency register for the device using a BIOS/platform driver. The mapping can be achieved using an advanced configuration and power interface device description.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cooper, Barnes Tigard, US 119 3049
Idan, Nevo Zichron Ya'akov, IL 7 15
Jeyaseelan, Jaya L Cupertino, US 31 535
Nalawadi, Rajeev El Dorado Hills, US 6 127
Poisner, David Carmichael, US 29 484
Varma, Suraj Portland, US 2 3
Weyhing, Linda Ann Arbor, US 1 3

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