Soft pin insertion during physical design
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United States of America Patent
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Jul 15, 2014
Grant Date -
Jul 3, 2014
app pub date -
Jan 2, 2013
filing date -
Jan 2, 2013
priority date (Note) -
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status (Latency Note)
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Abstract
A netlist for an integrated circuit design is constrained by virtual or “soft” pins to control or stabilize the placement of logic such as an architectural logic path. One soft pin is inserted at a fixed location proximate an input net of the path and is interconnected with the input net, and another is inserted at a fixed location proximate the output net and is interconnected with the output net. Cell placement is then optimized while maintaining the virtual pins at their fixed locations. More than two virtual pins may be inserted to bound a cluster of logic. The virtual pins may lie along the input/output nets. Pseudo-net weights are assigned to pseudo-nets formed between a cell and the virtual pins, and the pseudo-net weight can be increased for each placement iteration.
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