FinFET and method of fabrication
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United States of America Patent
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Mar 17, 2015
Grant Date -
Jul 10, 2014
app pub date -
Jan 9, 2013
filing date -
Jan 9, 2013
priority date (Note) -
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Abstract
An improved finFET and method of fabrication is disclosed. Embodiments of the present invention take advantage of the different epitaxial growth rates of {110} and {100} silicon. Fins are formed that have {110} silicon on the fin tops and {100} silicon on the long fin sides (sidewalls). The lateral epitaxial growth rate is faster than the vertical epitaxial growth rate. The resulting merged fins have a reduced merged region in the vertical dimension, which reduces parasitic capacitance. Other fins are formed with {110} silicon on the fin tops and also {110} silicon on the long fin sides. These fins have a slower epitaxial growth rate than the {100} side fins, and remain unmerged in a semiconductor integrated circuit, such as an SRAM circuit.
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