Instruction and logic to provide vector loads with strides and masking functionality

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United States of America Patent

PATENT NO 9672036
APP PUB NO 20140195775A1
SERIAL NO

13977730

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Abstract

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Instructions and logic provide vector loads and/or stores with stride and mask functionality. Some embodiments, responsive to an instruction specifying: a set of loads, destination register, mask register, memory address, and stride length; execution units read values in the mask register, wherein fields in the mask register correspond to stride-length multiples from the memory address to data elements in memory. A first mask value indicates the element has not been loaded from memory and a second value indicates that the element does not need to be, or has already been loaded. For each having the first value, the corresponding multiple of said stride length is generated according to the data field's position in the mask register to load the data element from memory into the corresponding destination register location, and the corresponding value in the mask register is changed to the second value. These instructions can restart after faults.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Doshi, Kshitij A Chandler, US 143 1037
Ould-Ahmed-Vall, Elmoustapha Chandler, US 573 3571
Sair, Suleyman Chandler, US 33 429
Yount, Charles R Phoenix, US 21 256

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