Debug control circuit
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United States of America Patent
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Dec 6, 2016
Grant Date -
Jul 17, 2014
app pub date -
Mar 18, 2014
filing date -
Mar 25, 2009
priority date (Note) -
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status (Latency Note)
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Abstract
A method and apparatus store a command in a command register and set, with a control circuit, a first operation mode associated with a split transaction for freeing a bus in a time period between a command transfer request and a command transfer operation. The method and apparatus set, with the control circuit, a second operation mode in which a split transaction is not issued and transfer, with the control circuit, the command to a processing unit via the bus in response to the command transfer request when in the second operation mode where after the processing unit executes the command and issues a subsequent command transfer request to the control circuit, the control circuit performs the split transaction when in the first and second operation modes.
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