Defect analysis system for error impact reduction
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United States of America Patent
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Nov 24, 2015
Grant Date -
Jul 17, 2014
app pub date -
Jan 14, 2013
filing date -
Jan 14, 2013
priority date (Note) -
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Abstract
An apparatus includes a network interface, memory, and a processor. The processor is coupled with the network interface and memory. The processor is configured to analyze a first set of data associated with a plurality of data sources. Analyzing the first set of data associated with the plurality of data sources determines a plurality of relationships among the first set of data. The processor is configured to store indications of the plurality of relationships among the first set of data. An indication of a relationship indicates a possible software defect. The processor is configured to generate rules based, at least in part, on the first set of data associated with a plurality of data sources. A rule indicates a possible software defect.
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