Error protection for a data bus

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United States of America Patent

PATENT NO 9201727
APP PUB NO 20140201606A1
SERIAL NO

13741599

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Abstract

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A system for providing error detection or correction on a data bus includes one or more caches coupled to a central processing unit and to a hub by one or more buses. The system also includes a plurality of arrays, each array disposed on one of the buses. Each of the arrays includes a plurality of storage cells disposed in an insensitive direction and an error control mechanism configured to detect an error in the plurality of storage cells.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Huott, William V Holmes, US 84 508
Kark, Kevin W Poughkeepsie, US 28 517
Massey, John G Jericho, US 15 44
Muller, K Paul Wappingers Falls, US 62 947
Rude, David L Wendell, US 8 29
Wolpert, David S Poughkeepsie, US 14 46

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