Electrical connection with reduced topography
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United States of America Patent
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Aug 23, 2016
Grant Date -
Jul 31, 2014
app pub date -
Jan 30, 2013
filing date -
Jan 30, 2013
priority date (Note) -
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Abstract
The formation of substrate electrical connections on thin film heads is one source of resulting surface topography. In accordance with one implementation, such topography can be reduced by a process that includes depositing a first layer of basecoat, creating electrical recessed vias in one or more plating processes, and depositing a second layer of basecoat on top of the electrical vias and on top of the first layer of basecoat. In one implementation, the first and second layers of basecoat have a combined height that is substantially equal to the height of the electrical recessed vias. In one implementation, the resulting topographical features are small enough that they can be planarized without creating a lack of uniformity in the total basecoat thickness across the wafer.
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