Using modeling to determine wafer bias associated with a plasma system
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Nov 22, 2016
Grant Date -
Jul 31, 2014
app pub date -
Jan 31, 2013
filing date -
Jan 31, 2013
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Systems and methods for determining wafer bias are described. One of the methods includes detecting output of a generator to identify a generator output complex voltage and current (V&I). The generator is coupled to an impedance matching circuit and the impedance matching circuit is coupled to an electrostatic chuck (ESC). The method further includes determining from the generator output complex V&I a projected complex V&I at a point along a path between an output of a model of the impedance matching circuit and a model of the ESC. The operation of determining of the projected complex V&I is performed using a model for at least part of the path. The method includes applying the projected complex V&I as an input to a function to map the projected complex V&I to a wafer bias value at the ESC model.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully