Variable read latency on a serial memory bus

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United States of America Patent

PATENT NO 10303625
APP PUB NO 20140215111A1
SERIAL NO

14228384

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Abstract

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Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer.

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Patent Owner(s)

  • CYPRESS SEMICONDUCTOR CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Zitlaw, Clifford Alan San Jose, US 17 189

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