NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
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United States of America Patent
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Issued Date -
Aug 14, 2014
app pub date -
Mar 14, 2013
filing date -
Feb 11, 2013
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
According to one embodiment, a memory cell includes a gate insulating layer on the active area, a floating gate electrode on the gate insulating layer, the floating gate electrode having a lower portion with a first width and a higher portion with a second width narrower than the first width, an intermediate insulating layer covering an end of the higher portion of the floating gate electrode, a charge storage layer being adjacent to the intermediate layer, an inter-electrode insulating layer covering the floating gate electrode and the charge storage layer, and a control gate electrode on the inter-electrode insulating layer.
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