Programmable logic device and semiconductor device

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8952723
APP PUB NO 20140225644A1
SERIAL NO

14166936

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Abstract

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To provide a PLD having a reduced circuit area and an increased operation speed. In the circuit structure, a gate of a transistor provided between an input terminal and an output terminal of a programmable switch element is in an electrically floating state in a period when a signal is input to the programmable switch element. The structure enables the voltage of a gate to be increased by a boosting effect in response to a signal supplied from programmable logic elements, suppressing a reduction in amplitude voltage. This can reduce a circuit area by a region occupied by a booster circuit such as a pull-up circuit and increase operation speed.

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Patent Owner(s)

  • SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Aoki, Takeshi Kanagawa, JP 256 2614
Ikeda, Takayuki Kanagaawa, JP 384 4217
Kozuma, Munehiro Kanagawa, JP 118 1035
Kurokawa, Yoshiyuki Kanagawa, JP 517 7021

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