APPARATUS AND METHOD TO REDUCE BIT LINE DISTURBS
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United States of America Patent
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Issued Date -
Aug 21, 2014
app pub date -
Feb 18, 2013
filing date -
Feb 18, 2013
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Abandoned
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Abstract
A non-volatile memory device comprising a memory cell array including a plurality of non-volatile memory cells arranged in rows and columns, wherein memory cells arranged in a same row share a word line and memory cells arranged in a same column share a bit line; and at least an address decoder to provide a negative voltage to at least one non-accessed word line in said array when a programming or erasure voltage is provided along a shared bit line.
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