Highly Efficient Design of Storage Array Utilizing Multiple Cache Lines for Use in First and Second Cache Spaces and Memory Subsystems

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United States of America Patent

SERIAL NO

14187539

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Abstract

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A method of operating a cache memory includes the step of storing a set of data in a first space in a cache memory, a set of data associated with a set of tags. A subset of the set of data is stored in a second space in the cache memory, the subset of the set of data associated with a tag of a subset of the set of tags. The tag portion of an address is compared with the subset of data in the second space in the cache memory in that said subset of data is read when the tag portion of the address and the tag associated with the subset of data match. The tag portion of the address is compared with the set of tags associated with the set of data in the first space in cache memory and the set of data in the first space is read when the tag portion of the address matches one of the sets of tags associated with the set of data in the first space and the tag portion of the address and the tag associated with the subset of data in the second space do not match.

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Patent Owner(s)

Patent OwnerAddress
NARADA SYSTEMS LLCALLEN TX

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kavipurapu, Gautam Nag Allen, US 11 62

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