GENERATION OF MULTIPLE DIAMETER NANOWIRE FIELD EFFECT TRANSISTORS
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United States of America Patent
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app pub date -
Apr 17, 2013
filing date -
May 12, 2010
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Abandoned
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Abstract
A system is provided and includes a wafer and a mask. The wafer includes a silicon-on-insulator (SOI) structure disposed on a buried oxide (BOX) layer and has a first region with a first SOI thickness and a second region with a second SOI thickness, the first and second SOI thicknesses being different from one another and sufficiently large such that respective pairs of SOI pads connected via respective nanowires with different thicknesses are formable therein. The mask covers one of the first and second regions and prevents a thickness change of the other of the first and second regions from having effect at the one of the first and second regions.
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