Semiconductor chip including region having cross-coupled transistor configuration with offset electrical connection areas on gate electrode forming conductive structures and at least two different inner extension distances of gate electrode forming conductive structures
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United States of America Patent
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Sep 30, 2014
Grant Date -
Aug 28, 2014
app pub date -
May 8, 2014
filing date -
Mar 13, 2008
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Abstract
A first linear-shaped conductive structure (LCS) forms a gate electrode (GE) of a first transistor of a first transistor type. A second LCS forms a GE of a first transistor of a second transistor type. A third LCS forms a GE of a second transistor of the first transistor type. A fourth LCS forms a GE of a second transistor of the second transistor type. Each of the first, second, third, and fourth LCS's has a respective electrical connection area. The electrical connection areas of the first and third LCS's are offset from each other. The GE of the first transistor of the first transistor type is electrically connected to the GE of the second transistor of the second transistor type. The GE of the second transistor of the first transistor type is electrically connected to the GE of the first transistor of the second transistor type.
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