Nonvolatile semiconductor memory device and method of controlling same
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United States of America Patent
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Oct 6, 2015
Grant Date -
Aug 28, 2014
app pub date -
Sep 4, 2013
filing date -
Feb 26, 2013
priority date (Note) -
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Abstract
The disclosure describes a semiconductor memory device including a memory cell array and a control circuit. The memory cell array comprises a plurality of memory cells that each include a control gate and a charge accumulation layer and that each are configured to have a threshold set to be included in any of a plurality of threshold distributions, the memory cell being connected between a bit line and a source line. The control circuit, in at least one of a write verify operation and a read operation on a selected memory cell, applies to the control gate a control gate voltage to determine the threshold of the selected memory cell, the control gate voltage having a plurality of values respectively corresponded to the plurality of threshold distributions, and sets a voltage between the bit line and the source line based on the control gate voltage.
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