SEMICONDUCTOR MEMORY
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United States of America Patent
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Issued Date -
Aug 28, 2014
app pub date -
Aug 1, 2013
filing date -
Feb 28, 2013
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
According to one embodiment, a semiconductor memory includes a memory cell unit, an encoding circuit that generates a first parity and a second parity for data, and a decoding circuit that performs error correction by using the data, the first parity, and the second parity, the first parity is generated by using a first generation polynomial for the data, the second parity is generated by using a second generation polynomial for the input data and the first parity, the second generation polynomial is selected based on the first generation polynomial, the data and the first parity is output to the outside, and the second parity is not output to the outside.
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