Programmable Leakage Test For Interconnects In Stacked Designs
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United States of America Patent
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app pub date -
Mar 3, 2014
filing date -
Mar 1, 2013
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Abandoned
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Abstract
Aspects of the invention relate to techniques of testing interconnects in stacked designs for leakage defects. Logic “1” or “0” is first applied to one end of an interconnect during a first pulse. Then, logic value at the one end is captured, which triggered by an edge of a second pulse. The first pulse precedes the second pulse by a time period being selected from a plurality of delay periods. The plurality of delay periods is generated by a device shared by a plurality of interconnects.
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