Thermally-optimized metal fill for stacked chip systems
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United States of America Patent
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Jun 16, 2015
Grant Date -
Sep 4, 2014
app pub date -
Mar 1, 2013
filing date -
Mar 1, 2013
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Abstract
Stacked chip systems and design structures for stacked chip systems, as well as methods and computer program products for placing thermal conduction paths in a stacked chip system. The method may include determining an availability of space in a layout of an interconnect structure of a first chip for a fill shape structure extending partially through the interconnect structure to thermally couple a metal feature in the interconnect structure with a bonding layer between the interconnect structure of the first chip and a second chip. If space is available, the fill shape structure may be placed in the layout of the interconnect structure of the first chip. The stacked chip system may include the first and second chips, the bonding layer between the interconnect structure of the first chip and the second chip, and the fill shape structure.
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