Data transfer operation completion detection circuit and semiconductor memory device provided therewith
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United States of America Patent
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Mar 31, 2015
Grant Date -
Sep 4, 2014
app pub date -
May 16, 2014
filing date -
Sep 20, 2005
priority date (Note) -
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Abstract
A data transfer operation completion detection circuit including a first counter for performing a shifting operation in response to the generation of a read initiation signal, a second counter for performing a shifting operation in response to the generation of a burst completion signal, and an SR latch circuit for generating a read enable signal in response to the burst completion signal being generated when the count value of the first counter matches the count value of the second counter. The completion of a read operation or another data transfer operation is thus detected based on a read initiation signal reception history; therefore, it is possible to detect whether all read operations are complete at a given time even if a new read command is received while a read operation or the like is in progress.
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