Mitigating electromigration effects using parallel pillars
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United States of America Patent
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Jan 12, 2016
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app pub date -
Mar 5, 2013
filing date -
Mar 5, 2013
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Abstract
Systems, methods, and other embodiments associated with an integrated circuit that includes a plurality of parallel pillar structures is described. In one embodiment, a system includes a design logic configured to analyze a design of an integrated circuit to identify open tracks on each layer by determining a location of structures in each layer of the design. The open tracks are spaces on each layer of the design that are free from structures that obstruct routing the plurality of pillar metals. The system also includes routing logic configured to successively route the plurality of pillar metals in each of the layers of the design based, at least in part, on the parameters and the location of the structures. The routing logic routes pillars of the plurality of pillar metals that are in adjacent layers to be perpendicular and pillar metals that are within a same layer of the design to be parallel.
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