Importance

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Abstract

Methods for reducing power consumption of a non-volatile storage system and reducing first read latency are described. The non-volatile storage system may include a cross-point memory array. In some embodiments, during a standby mode, the memory array may be biased such that both word lines and bit lines are set to ground. During transition of the memory array from the standby mode to a read mode, a selected word line comb may be set to a read voltage while the unselected word lines and the bit lines remain at ground. During the read mode, memory cells connected to the selected bit lines and the selected word line comb may be sensed while the selected bit lines are biased to a selected bit line voltage equal to or close to ground and the unselected bit lines are left floating after initially being set to ground.

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First Claim