Pipelining in a memory
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United States of America Patent
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Sep 22, 2015
Grant Date -
Sep 11, 2014
app pub date -
Mar 8, 2013
filing date -
Mar 8, 2013
priority date (Note) -
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Abstract
A system including a memory cell array including a plurality of memory cells, and a writing device to generate multiple back-to-back write pulses to write to target memory cells from among the plurality of memory cells, the multiple back-to-back write pulses overlapping during an overlap duration, the overlap duration being adjustable based on a performance parameter of the memory cell array.
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