Local evaluation circuit for static random-access memory

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United States of America Patent

PATENT NO 8837235
SERIAL NO

13786860

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Abstract

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A local evaluation circuit for a memory array includes first and second NAND gates and first, second, third, and fourth switches. The first switch is configured to couple a first node of the second NAND gate to a first power supply node in response to a first read signal. The second switch is configured to couple a first node of the first NAND gate to the first power supply node in response to a second read signal. The third switch is configured to couple a second node of the first NAND gate to a second power supply node in response to the first read signal. The fourth switch is configured to couple a second node of the second NAND gate to the second power supply node in response to the second read signal.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chan, Yuen Hung Poughkeepsie, US 20 112
Kugel, Michael Boeblingen, DE 15 36
Penth, Silke Holzgerlingen, DE 14 22
Werner, Tobias Schoenbuch, DE 46 343

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