Memory controller and memory system
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United States of America Patent
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Nov 17, 2015
Grant Date -
Sep 11, 2014
app pub date -
Sep 11, 2013
filing date -
Mar 11, 2013
priority date (Note) -
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Abstract
A memory controller having a plurality of channels according to an embodiment of the present invention includes: a valid page information management unit that manages, for each of the channel, identification information of a valid page; a write buffer that stores data to be written to the memory; a garbage collection control unit that executes a garbage collection process; and a channel controller capable of executing multi-plane read. The garbage collection control unit controls multi-plane read of the channel controller based on the identification information to level a total number of valid pages read from each of the channel.
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