MEMORY CONTROLLERS INCLUDING TEST MODE ENGINES AND METHODS FOR REPAIR OF MEMORY OVER BUSSES USED DURING NORMAL OPERATION OF THE MEMORY
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United States of America Patent
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Issued Date -
Sep 11, 2014
app pub date -
Mar 5, 2013
filing date -
Mar 5, 2013
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Abstract
Examples of memory controllers are described that may repair a memory using a bus between the memory controller and the memory. The memory controllers may include a test mode engine able to place the memory into a test mode of operation using a combination of signals over the bus, which combination of signals may be illegal in normal operation. The memory system controllers may include a BIST engine for testing the memory and obtaining information regarding memory fail information. The test mode engines may be configured to adjust a clock frequency during the test mode of operation, including stopping a clock signal in some examples between test mode commands.
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