Built-in-self-test (BIST) test time reduction

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United States of America Patent

PATENT NO 9773570
SERIAL NO

13786572

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Aspects of the invention provide for reducing BIST test time for a memory of an IC chip. In one embodiment, a BIST architecture for reducing BIST test time of a memory for an integrated circuit (IC) chip, the architecture comprising: a pair of latches for receiving bursts of data from a memory; a first compression stage for receiving a burst of data and compressing the burst of data into a plurality of latches; a second compression stage for comparing the compressed bursts of data with expected data; and a logic gate for determining whether there is a fail in the burst of data.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gorman, Kevin W Fairfax, US 48 1208
Hanagandi, Deepak I Karnataka, IN 12 45
Mondal, Krishnendu Bangalore, IN 22 168
Ouellette, Michael R Westford, US 115 1009

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