Formation of bulk SiGe fin with dielectric isolation by anodization
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United States of America Patent
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Mar 10, 2015
Grant Date -
Sep 18, 2014
app pub date -
Mar 14, 2013
filing date -
Mar 14, 2013
priority date (Note) -
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status (Latency Note)
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Abstract
A method of fabricating a semiconductor device is provided that includes providing a material stack that includes a silicon layer, a doped semiconductor layer, and an undoped silicon germanium layer. At least one fin structure is formed from the material stack by etching through the undoped silicon germanium layer, the doped semiconductor layer, and etching a portion of the silicon-containing layer. An isolation region is formed in contact with at least one end of the at least one fin structure. An anodization process removes the doped semiconductor layer of the at least one fin structure to provide a void. A dielectric layer is deposited to fill the void that is present between the silicon layer and the doped semiconductor layer. Source and drain regions are then formed on a channel portion of the at least one fin structure.
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