Continuous-time oversampling pipeline analog-to-digital converter
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United States of America Patent
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Nov 25, 2014
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app pub date -
Apr 24, 2013
filing date -
Mar 15, 2013
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Abstract
A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.
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