Systems and methods for estimation of offset and gain errors in a time-interleaved analog-to-digital converter
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United States of America Patent
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Oct 6, 2015
Grant Date -
Sep 18, 2014
app pub date -
Mar 13, 2014
filing date -
Mar 15, 2013
priority date (Note) -
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Abstract
The present disclosure relates to the field of background estimation in a time-interleaved analog-to-digital converter (ADC). More specifically, the present disclosure relates to systems and methods for background estimation of offset and gain errors in a time-interleaved ADC based on sample count. The error estimation unit of the time-interleaved ADC system includes a counting unit, a subtractor and an integrator. The method for estimating an offset error in a time-interleaved ADC includes determining signs of the signals and outputting corresponding values by the counting unit. The values are further compared and integrated to estimate the offset error. The method for estimating a gain error in a time-interleaved ADC includes determining the absolute values of the signals and comparing the absolute values with a predetermined threshold value. The comparison results are further integrated to estimate the gain error.
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