Nonvolatile semiconductor memory device
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United States of America Patent
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Nov 11, 2014
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app pub date -
Sep 10, 2013
filing date -
Mar 15, 2013
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Abstract
A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array that includes NAND cell units; and a write/erase circuit configured to execute a select gate write operation, the select gate write operation executing a programming operation for setting a threshold voltage of a drain side select gate and a verify operation for judging whether said threshold voltage has reached a certain value, and, when it is judged by the verify operation on the drain side select gate that the threshold voltage of the drain side select gate has not reached the certain value, repeatedly executing a programming operation for setting a threshold voltage of a drain side dummy cell connected to the drain side select gate and a verify operation for judging whether said threshold voltage has reached a certain value, until the threshold voltage of the drain side dummy cell has reached the certain value.
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