Non-volatile semiconductor memory device
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United States of America Patent
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Mar 17, 2015
Grant Date -
Sep 18, 2014
app pub date -
May 30, 2014
filing date -
Mar 25, 2011
priority date (Note) -
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Abstract
When performing a data erase operation, the control circuit generates positive holes at least at any one of the drain side select transistor and the source side select transistor, and supply the positive holes to a body of the memory string to raise a voltage of the body of the memory string to a first voltage. Then, it applies a voltage smaller than the first voltage to a first word line among the plurality of the word lines during a first time period. In addition, it applies a voltage smaller than the first voltage to a second word line different from the first word line during a second time period.
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