Methods and apparatus for reducing programming time of a memory cell
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United States of America Patent
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Dec 1, 2015
Grant Date -
Sep 18, 2014
app pub date -
May 29, 2014
filing date -
Aug 31, 2009
priority date (Note) -
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Abstract
A method is provided for programming a memory cell having a first terminal coupled to a word line and a second terminal coupled to a bit line. During a first predetermined time interval, the word line is switched from a first standby voltage to a first voltage, the bit line is switched from a second standby voltage to a predetermined voltage, and a voltage drop across the first and second terminals is a safe voltage that does not program the memory cell. During a second predetermined time interval, the word line is switched from the first voltage to a second voltage, and a voltage drop across the first and second terminals is a programming voltage that is sufficient to program the memory cell. Numerous other aspects are provided.
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