Delay timer device, method for managing a plurality of delays, and apparatus for delaying a plurality of data packets
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jul 12, 2016
Grant Date -
Sep 18, 2014
app pub date -
May 29, 2014
filing date -
Nov 29, 2011
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An embodiment delay timer for timing a plurality of delays includes a delay clock comprising a number of clock memories, wherein the number of clock memories corresponds to a number of digit positions of a delay clock value, and a delay memory configured to store the plurality of delays. The delay timer further includes a delay logic unit configured to add a new delay by storing it in the delay memory and to time the new delay by coupling it to that clock memory which corresponds to the most significant digit position of the delay value of the new delay that is not zero, by subsequently coupling the new delay to that clock memory which corresponds to the next less significant digit position of the delay value according to the delay value of the new delay and by generating a delay signal when the new delay expires.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully