Semiconductor chip with adaptive BIST cache testing during runtime

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United States of America Patent

PATENT NO 9229872
APP PUB NO 20140281254A1
SERIAL NO

13843639

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Abstract

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A method is described that includes during runtime of a semiconductor die, determining that a next BIST test sequence of a storage component embedded on the die is appropriate. The method further includes applying a BIST test sequence to each valid entry in the storage component. The method also includes marking any newly invalid entries in the storage component as invalid and configuring a respective replacement entry for each of the newly invalid entries.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kwan, Kelvin Santa Clara, US 8 36
Nasrullah, Jawad Palo Alto, US 23 249
Wilkerson, Christopher Portland, US 13 107

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