Volatile memory storing system data during low power mode operation and monitoring the voltage supplied to the memory during low power mode
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United States of America Patent
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May 10, 2016
Grant Date -
Sep 18, 2014
app pub date -
Mar 15, 2013
filing date -
Mar 15, 2013
priority date (Note) -
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Abstract
Apparatus and method for operating a device in a low power mode. In accordance with some embodiments, the apparatus comprises a memory and a system on chip (SOC) integrated circuit. The SOC has a first region with a processing core and a second region electrically isolated from the first region as an always on domain power island with a power control block. In response to a sleep command, the processing core transfers system data to the memory and the power control block enters a low power mode in which no electrical power is supplied to the first region. In response to a wake up command, power is restored to the first region and the processing core performs a reinitialization operation responsive to status information communicated by the power control block indicative of a state of the system during the low power mode.
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