Data integrity management in memory systems

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 9354973
APP PUB NO 20140281813A1
SERIAL NO

13798370

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Data management logic allocates a portion such as a single plane of a respective multi-plane non-volatile memory device to store parity information for corresponding data striped across multiple planes of multiple non-volatile memory devices. According to one configuration, the data management logic as discussed herein generates parity data based on (a data stripe of) non-parity data stored in multiple planes of multiple different memory devices. The data management logic stores the parity data in the storage plane allocated to store the parity information. Additional configurations include: reserving a parity block amongst multiple non-parity data blocks to store parity data and reserving a parity page amongst multiple non-parity data pages to store parity data.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Frickey, Robert E Sacramento, US 10 55
Guo, Xin San Jose, US 447 3807
Wakchaure, Yogesh B Folsom, US 37 363

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