Processor scheduling with thread performance estimation on cores of different types

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United States of America Patent

PATENT NO 9286128
APP PUB NO 20140282565A1
SERIAL NO

13843496

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Abstract

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A processor is described having an out-of-order core to execute a first thread and a non-out-of-order core to execute a second thread. The processor also includes statistics collection circuitry to support calculation of the following: the first thread's performance on the out-of-order core; an estimate of the first thread's performance on the non-out-of-order core; the second thread's performance on the non-out-of-order core; an estimate of the second thread's performance on the out-of-order core.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Emer, Joel Hudson, US 12 296
Jaleel, Aamer Cambridge, US 23 547
Narvaez, Paolo Wayland, US 25 656
Van, Craeynest Kenzo Hudson, US 2 60

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