Transient Voltage Suppressor, Design and Process

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United States of America Patent

APP PUB NO 20140284659A1
SERIAL NO

14222233

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Abstract

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A transient voltage suppressor (TVS) device design compatible with normal IC wafer process is provided. Instead of a thick base that requires double-sided wafer processing, a much thinner base with a modulated doping profile is used. In this base, a high doping layer is sandwiched by two lower layers of the same or different doping. The base is then sandwiched by two electrodes having opposite doping relative to the base center layer. In the base, the two lower doping layers will determine the breakdown voltage. The middle layer is used to reduce the transistor gain and thus produce an acceptable snapback characteristic. The presence of the higher doped middle layer allows the total base width to be as low as 5 μm for a breakdown voltage of about 30 V.

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Patent Owner(s)

Patent OwnerAddress
BOURNS INC1200 COLUMBIA AVENUE RIVERSIDE CA 92507

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Morrish, Andrew J Saratoga, US 39 269
Wei, Tao Los Gatos, US 110 574

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