SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
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United States of America Patent
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Issued Date -
Sep 25, 2014
app pub date -
Sep 3, 2013
filing date -
Mar 22, 2013
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
Plural first charge accumulation layers are arranged on a first gate-insulating film, and divided in the first direction and the second direction. Plural second charge accumulation layers are arranged on a second gate-insulating film and divided in the first direction and the second direction. An intermediate insulating film is arranged on the side surface of the first charge accumulation layers and on the side surface of the second charge accumulation layers. The control electrode includes a side-surface portion, which is arranged on the side surface of the intermediate insulating film, extends in the second direction, and faces via the intermediate insulating film to the side surface of the first charge accumulation layer and the side surface of the second charge accumulation layer, and a pad portion arranged monolithically on the lower portion of the side-surface portion and having a width larger than the film thickness of the side-surface portion.
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