MEMORY CIRCUIT AND METHOD OF FORMING THE SAME USING REDUCED MASK STEPS

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United States of America Patent

SERIAL NO

14264918

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Abstract

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Disclosed is a memory circuit and method of forming the same. The memory circuit comprises a lower metallization layer defining first conducting lines. A continuous magnetic storage element stack is atop the lower metallization layer wherein a bottom electrode of the stack is in direct contact with the first conducting lines. An upper metallization layer is atop the continuous magnetic storage element stack, the upper metallization layer defining second conducting lines, which are in direct contact with said continuous magnetic storage element stack. Localized areas of the continuous magnetic storage element stack define discrete magnetic bits, each energizable through a selected pair of the first and second conducting lines. In a second aspect and a third aspect, the continuous magnetic storage element stack is respectively partially and fully etched through a single mask, to define the discrete magnetic bits.

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Patent Owner(s)

Patent OwnerAddress
III HOLDINGS 1 LLC2711 CENTERVILLE RD SUITE 400 WILMINGTON DE 19808

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Mani, Krishnakumar San Jose, US 54 185

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