Processing unit and error processing method
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United States of America Patent
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Feb 9, 2016
Grant Date -
Sep 25, 2014
app pub date -
Mar 6, 2014
filing date -
Mar 25, 2013
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A processing unit of the embodiments includes an instruction memory that holds a plurality of instructions specified by addresses, and that cannot execute read and write operations concurrently, an error correction circuit that detects and corrects an error in the instruction, a program counter, an instruction buffer that holds the instruction corrected as a corrected instruction, a program counter buffer that holds an address of the instruction where an error has been detected, a selector that selects and outputs any of the output of the error correction circuit and the output of the instruction buffer, and a control unit that controls the read and write of the instruction specified by the address from and into the instruction memory. The control unit writes the corrected instruction in the instruction memory using an address held in the program counter buffer when a predetermined condition is satisfied after the occurrence of the error.
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