Importance

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Abstract

Certain embodiments provide a semiconductor integrated circuit comprising: a logic circuit including combination circuits and first flip-flops; plural selectors for respective first flip-flops configured to switch between first paths from the combination circuits and second paths from previous stage flip-flops of the first flip-flops; plural scan chains in the logic circuit, each of the scan chains configured to have the second path activated by the selectors; a pattern generator configured to generate patterns for test for the scan chains; a test control circuit configured to control the pattern generator and the plural selectors, the test control circuit performing self test; and plural setting terminals configured to set logic values individually in a combination of a part of second flip-flops which are representative of a logic pattern and of the first flip-flops in the logic circuit, the setting flip-flops being representative of a logic pattern.

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First Claim