FET semiconductor device with low resistance and enhanced metal fill
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United States of America Patent
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Jun 16, 2015
Grant Date -
Oct 2, 2014
app pub date -
Mar 28, 2013
filing date -
Mar 28, 2013
priority date (Note) -
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Abstract
In a method of fabricating a FET semiconductor device, a FET structure with a gate channel and dummy gate is formed on a layer of substrate. The gate channel includes one or more FINs, and spacer layers that line the sides of the gate channel and abut the layer of substrate. The dummy gate is removed and the height of the gate channel is reduced to substantially near that of a top surface of one or more FINs. A layer of high-k material is deposited into the gate channel. A layer of first metal is then deposited that fills the gate channel and covers, at least in part, the layer of high-k material. Excess material is removed from the layers of high-k material and first metal to create a surface. A layer of second metal is selectively deposited onto the surface to form a continued gate conductor.
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