Method and apparatus for reducing chip power consumption
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United States of America Patent
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Mar 1, 2016
Grant Date -
Oct 2, 2014
app pub date -
Apr 1, 2014
filing date -
Apr 1, 2013
priority date (Note) -
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Abstract
The present invention discloses a method for reducing chip power consumption. The method includes: monitoring real-time load statuses of an input interface, an output interface, and an internal bus of a chip, and collecting load monitoring information; adjusting a working frequency of the chip according to the load monitoring information; and performing rate limiting for an information transmission rate of each channel of the chip according to the current working frequency of the chip. The method and apparatus for reducing chip power consumption according to the present invention solve a problem in the prior art that in a process of chip frequency modulation and power consumption reduction, it is difficult to implement constant rate limiting for a chip channel, thereby providing a feasible solution for reducing chip power consumption while maintaining constant rate limiting for the chip channel.
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