Processor time synchronization apparatus and method in data communication system with multiple processors and line interfaces
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United States of America Patent
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Nov 8, 2016
Grant Date -
Oct 2, 2014
app pub date -
Nov 19, 2013
filing date -
Mar 29, 2013
priority date (Note) -
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Abstract
A processor time synchronization apparatus and method in a data communication system which includes a plurality of processors and line interfaces. The processor time synchronization apparatus includes a first local processor configured to recognize a time difference between an external device and the system based on a time message exchanged with the external device, and synchronize time between the external device and the system, and a second local processor configured to receive time information from the first local processor that has been time-synchronized with the external device, the time information containing the time difference between the external device and the system, and synchronize the first local processor with a system's internal time using the received time information.
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