Flip-flop with reduced retention voltage
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United States of America Patent
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Jun 6, 2017
Grant Date -
Oct 16, 2014
app pub date -
Apr 12, 2013
filing date -
Apr 12, 2013
priority date (Note) -
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status (Latency Note)
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Abstract
A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.
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